The Jedec Association completed the development of the HBM4 specification -the next generation of high transit memory. The updated standard is designed to meet the growing needs for data processing for tasks of artificial intelligence, machine learning and complex calculations. The new standard provides a double increase in the number of independent channels – up to 32 per stack, which improves parallel calculations and flexibility of access to data. The capacity reaches 2 TB/s due to the transmission speed of 8 GB/s due to a 2048-bit tire. This is 60% higher than that of the previous version of HBM3E.
Energy efficiency is increased by supporting different voltage levels (VDDQ and VDDC), so that energy consumption can be optimized, depending on tasks. In order to reduce the risks of malfunctions, the direct Refresh Management (DRFM) system has been introduced, which increases the reliability of the memory. HBM4 retains compatibility with HBM3 controllers, so that the transition to a new generation is simplified. The maximum capacity of one stack is 64 GB (16 layers of 32 Gbit), configurations with 4, 8 and 12 layers are also available.
According to experts, the massive use of HBM4 will start in commercial products by 2026. However, the first test samples for testing will appear at manufacturers in the coming months. This will accelerate the development of solutions for data processing centers, supercomputers and graphic accelerators. HBM4 is expected to become the basis for systems that require extreme performance, such as generative AI and large -scale modeling. The updated standard can also reduce the energy consumption of data centers by optimizing work with large amounts of data.
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Source: VG Times
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